Currently, many integrated circuits (ICs) include circuitry to generate reference voltages used by other components in the ICs. For example, a comparator in an IC may compare an input voltage to a reference voltage generated by a reference voltage circuitry in the same IC and further operations may be triggered in response to the result of the comparison. To improve the accuracy of the IC, a relatively stable reference voltage is desired. However, reference voltages generated in some conventional circuitry may vary significantly with temperature. For example, a reference voltage that corresponds to a difference between the threshold voltages of two transistors (a.k.a. delta threshold voltage reference) in an IC may vary with temperature because the overdrive (VGS-VTH) of both the transistors may not vary in an identical manner. In weak-inversion region of operation, this translates to the mobility variation with temperature of both the transistors may not be equal.
One conventional circuit to generate a reference voltage with reduced temperature dependence is shown in FIG. 1. The circuit 100 generates a first order bandgap reference voltage. Thus, the circuit 100 is also referred to as a first order bandgap reference voltage generating circuit. The circuit 100 includes two bipolar junction transistors (BJTs) Q1 and Q2, three resistors R1, R2, and R3, and an operational amplifier 130. The collectors of Q1 and Q2 are coupled together to the ground. The emitter of Q1 is coupled to one end of R1 at node 131, while the other end of R1 is coupled to node 190. The emitter of Q2 is coupled to one end of R3, while the other end of R3 is coupled to node 132. R2 is coupled between node 132 and node 190. A positive input of operational amplifier 130 is coupled to node 131 and a negative input of operational amplifier 130 is coupled to node 132. The voltages at nodes 131 and 132 are hereinafter referred to as V+ and V−, respectively. The output of operational amplifier 130 is coupled to node 190. A reference voltage (Vref) is output at node 190. The operation of the circuit 100 is described below.
In general, the operational amplifier 130 maintains V+ and V− to be substantially the same. Since the base and the collector of Q1 are coupled to the ground, V+ substantially equals to the emitter-base voltage of Q1, i.e., V+=VBE1. As for V−, the value of V− is the sum of the voltage across R3 and the emitter-base voltage of Q2, i.e., V−=I*R3+VBE2, where I is the current flowing through R3. Since V+ substantially equals to V−, VBE1=I*R3+VBE2, from which I is derived to be: I=(VBE1−VBE2)/R3=ΔVBE/R3, where ΔVBE=VBE1−VBE2. Vout is substantially equal to the sum of the voltages across R2, R3, and Q2. Therefore, Vout=I*(R2+R3)+VBE2. Substituting I with the expression derived above, Vout=(ΔVBE/R3)*(R2+R3)+VBE2. Note that VBE2 is complementary to absolute temperature (CTAT) and ΔVBE is proportional to absolute temperature (PTAT). By having a sum of VBE2 and scaled-up ΔVBE, a first order bandgap voltage that is substantially temperature independent may be generated.
However, the conventional technique described above suffers from many disadvantages. First, the circuit 100 consumes significant power because a minimum current is dictated by a current gain (β) of the bipolar junction transistors, typically of the order of 200 nA, which is used to bias Q1 and Q2 reliably. Also, the circuit 100 occupies an unreasonable amount of silicon area due to the usage of the resistors whose sheet resistance may be of the order of tens of ohms.
To reduce the impact of high power consumption, one conventional low power design of a bandgap voltage generator exploits the PTAT behavior of a set of n-type metal oxide semiconductor (NMOS) transistors operating in weak-inversion region. The output reference voltage is a function of the drain current, the shape factor, and the current gain (β) of the transistors. However, careful crafting is needed to produce a PTAT voltage because the low power design relies on cancellation of threshold voltages between transistors of the same type but with different shape factors. Moreover, the performance of the low power design may be dominated by the mismatch between the transistors.